1. Field
The present disclosure generally relates to repeater circuits. More specifically, the present disclosure relates to a repeater circuit that includes a phase interpolator, which is suitable for use in high-speed links.
2. Related Art
Clock forwarding is used in a wide variety of systems. As illustrated in FIG. 1, which presents a block diagram illustrating a system 100, during clock forwarding a data signal 108 and a clock signal 110 are typically output onto corresponding data signal line 116-1 and clock signal line 116-2 within a link 114 by a transmit circuit 112. Typically, data signal 108 has a higher fundamental frequency than clock signal 110.
At one or more locations 118 along link 114, repeater circuits 120 compensate for attenuation by amplifying data signal 108 and clock signal 110. For example, an internal clock signal, which has the same fundamental frequency as data signal 108, may be generated in repeater circuit 120-1 based on clock signal 110 using clock circuit 122. This internal clock signal may be used to synchronize amplification and recovery of data signal 108 by data-recovery circuit 124 because the low-frequency transmit jitter (such as flicker noise) in the internal clock signal is the same as the low-frequency transmit jitter in (forwarded) clock signal 110 and data signal 108. Note that by using such an internal clock signal, the tracking requirements for data-recovery circuit 124 may be reduced. In many cases, data recovery may be implemented with a static phase adjustment of the generated internal clock signal relative to data signal 108.
After amplification using a sense amplifier (SA) 126 and a clock amplifier 128, and data recovery using data-recovery circuit 124, the amplified data signal and an amplified clock signal are output onto link 114 by drivers 130 in repeater circuit 120-1. These signals may be subsequently received by a receive circuit 132 at the end of link 114 or by one or more optional additional repeater circuits 120 along link 114.
However, this type of repetitive clock forwarding can eventually contaminate the forwarded clock signal because of noise introduced by the clock amplifier(s) (such as clock amplifier 128) in repeater circuit(s) 120. Because of a time-slope conversion, this noise typically manifests itself as cycle-to-cycle jitter in the time domain.
Note that the cycle-to-cycle jitter can limit the number of repeater circuits 120 that can be used along link 114, and thus limits a total length 134 of link 114 at a given frequency. For example, the length of links based on copper cables (or cables that include another metal), such as in systems that communicate electrical signals which are compatible with an Ethernet communications protocol and/or an Infiniband communications protocol, is often restricted to less than 10 m. To address this difficulty, optical cables or fibers can be used. However, this increases the cost and complexity of these systems.
Hence, what is needed is a repeater circuit and an associated system that does not suffer from the above-described problems.